1. Field of the Invention
The present invention relates to an operation circuit used for a digital signal processor (DSP), more specifically to an operation circuit having a mode control function for a built-in multiplier.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration example of an operation means having a mode control function for a multiplier of a conventional digital signal processor, which is shown on Page 9 of the users' manual of the digital signal processor MSM 699210 manufactured by Oki Electric Industries Co., LTD. (February, 1988).
In FIG. 1, both numerals 101 and 102 designate registers for storing data which is to be operated, upon and an output of the register 101 is given to a multiplier 103 and a selector 104, and an output of the register 102 is given to the multiplier 103 and a selector 105.
The multiplier 103 executes mutual multiplication of data to be operated upon which are stored in the above-described registers 101 and 102, and multiplier outputs the result thereof to the selector 104. Whether the multiplier 103 executes fixed point multiplication or executes floating point multiplication at this time is specified by a mode control signal 202 being an output signal of a control register (CR) 201 given to the multiplier 103.
The control register 201 comprises a control bit controlling the operating mode of the multiplier 103. The value of a signal 203 specifies that a multiplication to be executed by the multiplier 103 is a fixed point multiplication or a floating point multiplication. In other words, signal 203 specifies the operating mode of the multiplier 103 in response to the contents of an instruction to be executed by the DSP comprising this operation circuit is determined by the control bit of the control register 201. Then, in correspondence to the value set in the control bit of the control register 201, the operating mode of the multiplier 103 is specified by the mode control signal 202.
The selector 104 selects either the output of the register 101 or the output of the multiplier 103, and gives it to an arithmetic logic unit (ALU) 106. The selector 105 selects either the output of the register 102 or the output of an accumulator 107 as described later, and gives it to the ALU 106.
The ALU 106 executes various arithmetic and logic operating with the outputs of the above-described selectors 104 and 105 taken as inputs, and outputs the results thereof to the accumulator 107.
The kind of operation, for example, fixed point operation, floating point operation or another operation, to be performed by the ALU 106 at this time is determined by the contents of the instruction to be executed by the DSP comprising this operation circuit, which will now be described.
An output of a decoder 108 is given to the ALU 106; an operation control signal 109. The decoder 108 decodes an operation specifying signal 113 according to a predetermined field for specifying an operation to be executed by the ALU 106 in the instruction to be executed by the DSP comprising this operation circuit, specifically an ALU operation specifying field, and gives the result thereof to the ALU 106 as the operation control signal 109.
Accordingly, the ALU 106 executes an operation specified by the operation control signal 109 with the outputs of the both selectors 104 and 105 as inputs, and accumulates the result thereof in the accumulator 107.
FIG. 2 is a schematic diagram showing the above-described field related to control of the multiplier 103 of the control register 201, and numeral 301 designates an MM flag stored in the above-described control bit.
FIG. 3 is a schematic diagram showing a function of the MM flag related to control of the multiplier 103 of the control register 201 as shown in FIG. 2. In the case where the value of the MM flag 301 is set to "1", the multiplier 103 is put in the fixed point multiplication mode, and executes fixed point multiplication. Also, in the case where the value of the MM flag 301 is set to "0", the multiplier 103 is put in the floating point multiplication mode, and executes floating point multiplication.
Hereinafter, description is made on operation of the conventional operation circuit having mode control function for multiplier configured as described above.
Specifying of the operation mode of the multiplier 103, that is, setting of the value of the MM flag 301 is performed by an instruction which sets the content of the control register 201.
First, in the case where fixed point multiplication is performed, the MM flag 301 of the control register 201 is set to "1" by an instruction. Thereby, the mode control signal 202 specifying fixed point multiplication is given to the multiplier 103 from the control register 201, and therefore the multiplier 103 is put in the fixed point multiplication mode, and executes mutual fixed point multiplication of data stored in the registers 101 and 102.
On the other hand, in the case where floating point multiplication is performed, the MM flag 301 of the control register 201 is set to "0" by an instruction. Thereby, the mode control signal 202 specifying floating point multiplication is given to the multiplier 103 from the control register 201, and therefore the multiplier 103 is put in the floating point multiplication mode, and executes mutual floating point multiplication of data stored in the registers 101 and 102.
The operation mode of the ALU 106, that is, the kind of operation to be executed by the ALU 106 is specified directly by an ALU operation specifying field specifying ALU operation in the instruction. The operation specifying signal 113 corresponding to this field is decoded by the decoder 108, and is given to the ALU 106 as the operation control signal 109. Then, the ALU 106 executes an operation specified by the operation control signal 109 for data given from the both selectors 104 and 105, and makes the accumulator 107 accumulate the result thereof.
Then, in the case where sum and product operation, is executed, the data formats of product and sum are the same, and therefore the multiplier 103 and the ALU 106 process data of the same format. This means that when fixed point multiplication is performed in the multiplier 103, fixed point operation is performed in the ALU 106, and when floating point multiplication is performed in the multiplier 103, floating point operation is performed in the ALU 106.
Then, in the operation circuit having mode control function for multiplier of the conventional DSP having the configuration as described above, the operation mode of the multiplier 103, that is, whether fixed point multiplication is to be performed or floating point multiplication is to be performed is specified by the MM flag 301 of the control register 201, and the operation mode of the ALU 106, that is, whether fixed point operation is to be performed or floating point operation is to be performed is specified by the ALU operation specifying field in the instruction. In other words, the operation modes of both of the multiplier 103 and the ALU 106 are specified independently in the instruction to be executed by the DSP. For this reason, in programming, a programmer is required to consider it while recognizing the operation mode of the multiplier 103 all the time, and therefore the efficiency of programming work is reduced. Also, an instruction is necessary which sets a bit equivalent to the content of the control register 201 for controlling the operation mode of the multiplier 103, specifically the MM flag 301.
In addition, there is a problem that the operation mode actually specified to the multiplier 103 cannot be checked in debugging.
Furthermore, there is another problem that in performing an interrupt or executing a subroutine call, the operation for maintaining the operation mode specified to the multiplier 103 in the same mode before and after the execution becomes complicated.